TLB Coalescing With Range Compressed Page Table for Embedded I/O Devices

Abstract

Modern embedded system on a chip (SoC) usually accommodates input/output (I/O) memory management units to support virtual memory. When a translation look-aside buffer (TLB) is miss, a page-table walk occurs and frequent page-table walks can significantly degrade the memory system performance. To improve TLB utilization, a number of TLB coalescing schemes have recently been reported. The TLB coalescing schemes exploit the contiguous memory allocation and can efficiently coalesce the contiguous virtual-to-physical page mappings into a single TLB entry. Accordingly, TLB coalescing schemes efficiently utilize TLB entries, reduce page-table walks, and can improve the memory system performance. However, the conventional page table is still organized in the page level and contains redundant page information. Subsequently, it is difficult for operating system to effectively represent the block-level contiguity in the page table and it is difficult for TLB coalescing hardware to exploit the contiguity. In this work, to improve the memory system performance, we propose a range compression technique in a page table. In the presented page-table entry, the redundant page attributes are removed and multiple block mappings are added. Considering high-bandwidth memory intensive mobile workloads, we conduct the performance experiments. As a result, the presented scheme can significantly perform better than the traditional scheme and the reference TLB coalescing schemes.

Keywords

• Page table
• compression
• address translation
• translation look-aside buffer
• memory management