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FPGA-based electrocardiography (ECG) signal analysis system using least-square linear phase finite impulse response (FIR) filter

Journal of Electrical Systems and Information Technology. 2016;3(3):513-526 DOI 10.1016/j.jesit.2015.07.001


Journal Homepage

Journal Title: Journal of Electrical Systems and Information Technology

ISSN: 2314-7172 (Online)

Publisher: SpringerOpen

Society/Institution: Electronics Research Institute (ERI)

LCC Subject Category: Technology: Electrical engineering. Electronics. Nuclear engineering | Technology: Technology (General): Industrial engineering. Management engineering: Information technology

Country of publisher: United Kingdom

Language of fulltext: English

Full-text formats available: PDF, HTML



Mohamed G. Egila (Microelectronics Department, Electronics Research Institute, Cairo, Egypt)

Magdy A. El-Moursy (Mentor Graphics Corporation, Cairo, Egypt)

Adel E. El-Hennawy (Communication and Electronics Department, Ain Shams University, Cairo, Egypt)

Hamed A. El-Simary (Microelectronics Department, Electronics Research Institute, Cairo, Egypt)

Amal Zaki (Microelectronics Department, Electronics Research Institute, Cairo, Egypt)


Double blind peer review

Editorial Board

Instructions for authors

Time From Submission to Publication: 9 weeks


Abstract | Full Text

This paper presents a proposed design for analyzing electrocardiography (ECG) signals. This methodology employs highpass least-square linear phase Finite Impulse Response (FIR) filtering technique to filter out the baseline wander noise embedded in the input ECG signal to the system. Discrete Wavelet Transform (DWT) was utilized as a feature extraction methodology to extract the reduced feature set from the input ECG signal. The design uses back propagation neural network classifier to classify the input ECG signal. The system is implemented on Xilinx 3AN-XC3S700AN Field Programming Gate Array (FPGA) board. A system simulation has been done. The design is compared with some other designs achieving total accuracy of 97.8%, and achieving reduction in utilizing resources on FPGA implementation.